1. | Course Title | Embedded System Design with FPGA | |||||||||||
2. | Code | 4ФЕИТ05023 | |||||||||||
3. | Study program | 9-VMS, 16-MNT, 18-ENEL, 19-MV, 22-BE | |||||||||||
4. | Organizer of the study program (unit, institute, department) | Faculty of Electrical Engineering and Information Technologies | |||||||||||
5. | Degree (first, second, third cycle) | Second cycle | |||||||||||
6. | Academic year/semester | I/1 | 7. | Number of ECTS credits | 6.00 | ||||||||
8. | Lecturer | Dr Katerina Raleva | |||||||||||
9. | Course Prerequisites | ||||||||||||
10. | Course Goals (acquired competencies):
This course gives the foundation of FPGA design for embedded systems using VHDL as a hardware description language. The students will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. |
||||||||||||
11. | Course Syllabus:
Digital VLSI design and the need for hardware description languages (HDL). Technologies for fabrication of integrated circuits. Programmable technologies. Complex programmable logic devices (CPLD) – architectures, programmable interconnections and macrocell structure. Field Programmable Gate Array (FPGA) – architecture, configuration logic blocs and switching matrix. Commercial FPGA architectures. VHDL structure – entity and architecture. Ports and signals. Concurrent and sequential statements. VHDL description of combinational and sequential logic. Simulation versus synthesis. Functions and procedures in VHDL. Finite State Machine Datapath design – optimization and implementation. Memory components and memory controllers. Distributed and embedded RAM in FPGA. Using IP Core (Intellectual Property)in FPGA design. Hierarchy in designing large digital systems. RTL (Register Transfer Level) design – definition, types of RTL design. Steps in RTL designing. Optimization of RTL design. RTL design with HDL. Synthesis and implementation of design. Hardware-software co-design. |
||||||||||||
12. | Learning methods:
lectures with presentations, homework and project assignment |
||||||||||||
13. | Total number of course hours | 180 | |||||||||||
14. | Distribution of course hours | 3 + 3 | |||||||||||
15. | Forms of teaching | 15.1 | Lectures-theoretical teaching | 45 hours | |||||||||
15.2 | Exercises (laboratory, practice classes), seminars, teamwork | 45 hours | |||||||||||
16. | Other course activities | 16.1 | Projects, seminar papers | 30 hours | |||||||||
16.2 | Individual tasks | 30 hours | |||||||||||
16.3 | Homework and self-learning | 30 hours | |||||||||||
17. | Grading | ||||||||||||
17.1 | Exams | 30 points | |||||||||||
17.2 | Seminar work/project (presentation: written and oral) | 50 points | |||||||||||
17.3. | Activity and participation | 20 points | |||||||||||
17.4. | Final exam | 0 points | |||||||||||
18. | Grading criteria (points) | up to 50 points | 5 (five) (F) | ||||||||||
from 51 to 60 points | 6 (six) (E) | ||||||||||||
from 61 to 70 points | 7 (seven) (D) | ||||||||||||
from 71 to 80 points | 8 (eight) (C) | ||||||||||||
from 81 to 90 points | 9 (nine) (B) | ||||||||||||
from 91 to 100 points | 10 (ten) (A) | ||||||||||||
19. | Conditions for acquiring teacher’s signature and for taking final exam | homework and project assignment | |||||||||||
20. | Forms of assessment | written tests and oral presentation of the final project | |||||||||||
21. | Language | Macedonian and English | |||||||||||
22. | Method of monitoring of teaching quality | Internal evaluation and surveys | |||||||||||
23. | Literature | ||||||||||||
23.1. | Required Literature | ||||||||||||
No. | Author | Title | Publisher | Year | |||||||||
1. | B. Mealy and F. Tappero | Free Range VHDL | http://www.freerangefactory.org | 2019 | |||||||||
2. | Clive Maxfield | The Design Warrior’s Guide to FPGA | Elsevier Inc | 2004 | |||||||||
23.2. | Additional Literature | ||||||||||||
No. | Author | Title | Publisher | Year | |||||||||
1. | Volnei A. Pedroni | Circuit Design and Simulation with VHDL | The MIT Press | 2010 | |||||||||
2. | Peter J. Ashenden | Digital Design: An Embedded System Approach using Verilog | Elsevier Inc. | 2008 |