1. Course Title | Advanced Computer Architectures | |||||||
2. Code | 4ФЕИТ07З012 | |||||||
3. Study program | КТИ,КХИЕ | |||||||
4. Organizer of the study program (unit, institute, department) | Faculty of Electrical Engineering and Information Technologies | |||||||
5. Degree (first, second, third cycle) | First cycle | |||||||
6. Academic year/semester | IV/7 | 7. Number of ECTS credits | 6 | |||||
8. Lecturer | D-r Danijela Efnusheva | |||||||
9. Course Prerequisites | Passed: Computer Architectures, Logic Design | |||||||
10. Course Goals (acquired competencies): Introduction to the functions of modern elements in advanced computer systems: various concepts for parallelism of instructions, synchronization of multiprocessors, modern design of memory hierarchy and practical examples. Upon completion of the course students will be able to: – analyze and understand advanced computer architectures; – understand techniques for achieving parallelism at instructional level, data level and thread level; – understand advanced processor architectures: vectors, super-scalars, VLIW processors, multi-issue processors, etc.; – understand parallel processors: multi-core processors with shared and distributed memory; – understand advanced memory technologies and optimization; – understand techniques for achieving memory coherence and synchronization in parallel processors; |
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11. Course Syllabus: Introduction to advanced computer architectures. Classes of computers and development directions. Trends in technology, price and power. Performances of computer systems. Quantitative approaches for design of computers. Instruction-level parallelism. Data and control dependences. Loop unrolling and scheduling. Branch prediction. Overcoming data hazards with dynamic scheduling. Tomasulo’s algorithm. Hardware-based speculative execution. Comparison of hardware versus software multiple instruction issue and speculation. Multithreading- a solution to the constraints of instruction level parallelism. Introduction to Intel Core i7 6700 and ARM Cortex-A53 processors. Multi-processor systems with shared memory and distributed memory. Synchronization. Maintaining memory consistency. Multi-core processors and their performance. Data-level parallelism. Vector processors. SIMD instruction set extensions for multimedia. Graphics processing units. Introduction to NVIDIA and Pascal GPU architecture. Comparison of graphics processors with other parallel processors. Memory hierarchy design. Memory technologies and optimizations. Optimizations of cache memory performances. Memory protection: virtual memory and virtual machines. Virtual machine monitor. Instruction set architecture support for virtual machines. Storage systems. I/O performance, reliability and testing. Design and evaluation of I/O system. | ||||||||
12. Learning methods: Lectures, tasks and exercises and laboratory practice | ||||||||
13. Total number of course hours | 2 + 2 + 1 + 0 | |||||||
14. Distribution of course hours | 180 | |||||||
15. Forms of teaching | 15.1. Lectures-theoretical teaching | 30 | ||||||
15.2. Exercises (laboratory, practice classes), seminars, teamwork | 45 | |||||||
16. Other course activities | 16.1. Projects, seminar papers | 0 | ||||||
16.2. Individual tasks | 25 | |||||||
16.3. Homework and self-learning | 80 | |||||||
17. Grading | 17.1. Exams | 0 | ||||||
17.2. Seminar work/project (presentation: written and oral) | 30 | |||||||
17.3. Activity and participation | 30 | |||||||
17.4. Final exam | 40 | |||||||
18. Grading criteria (points) | up to 50 points | 5 (five) (F) | ||||||
from 51to 60 points | 6 (six) (E) | |||||||
from 61to 70 points | 7 (seven) (D) | |||||||
from 71to 80 points | 8 (eight) (C) | |||||||
from 81to 90 points | 9 (nine) (B) | |||||||
from 91to 100 points | 10 (ten) (A) | |||||||
19. Conditions for acquiring teacher’s signature and for taking final exam | Practical (laboratory) exercises | |||||||
20. Forms of assessment | Two partial exams during the semester with a duration of 120 minutes or one full exam in a corresponding exam session with a duration of 120 minutes. Independent (seminar) project work by each student. The second partial exam includes presentation and defense of the (seminar) project work. The laboratory exercises are also graded. The final grade includes points from the exam, the project (seminar) work and the laboratory exercises. It is not allowed to use books, scripts, manuscripts or notes of any kind during the exam, as well as a calculator, mobile phone, tablet or any other electronic device. |
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21. Language | Macedonian and English | |||||||
22. Method of monitoring of teaching quality | Self-evaluation and questionnaires | |||||||
23. Literature | ||||||||
23.1. Required Literature | ||||||||
No. | Author | Title | Publisher | Year | ||||
1 | J. L. Hennessy, D.A. Patterson | Computer Architecture: A Quantitative Approach 6th Ed | Morgan Kaufmann | 2019 | ||||
2 | W. Stallings | Computer Organization and Architecture Designing for Performance 11th ed. | Pearson | 2019 | ||||
3 | Џон Л. Хенеси, Дејвид А. Петерсон | Компјутерска архитектура | Превод влада | 2011 | ||||
23.2. Additional Literature | ||||||||
No. | Author | Title | Publisher | Year | ||||
1 | D.A. Patterson, J. L. Hennessy | Computer Organization and Design The Hardware/Software Interface: RISC-V Edition | Morgan Kaufmann | 2018 | ||||
2 | Ендрју С. Таненбаум | Структурирана компјутерска организација | превод влада | 2012 |