Techniques for HDL Design and FPGA Implementation

Објавено: June 26, 2023
1. Course Title Techniques for HDL Design and FPGA Implementation
2. Code 4ФЕИТ12013
3. Study program 7-NKS
4. Organizer of the study program (unit, institute, department) Faculty of Electrical Engineering and Information Technologies
5. Degree (first, second, third cycle) Second cycle
6. Academic year/semester I/1   7.    Number of ECTS credits 6.00
8. Lecturer Dr Tatjana Nikolic
9. Course Prerequisites
10. Course Goals (acquired competencies):

Acquiring knowledge of designing digital electronic components in HDL – Hardware Description Languages. Acquiring knowledge of appropriate software environments for HDL design and simulation. Work with FPGA components.
11. Course Syllabus:

Digital systems design, implementation and application. HDL – Hardware Description Languages: VHDL, Verilog, System C. Using IP-cores for digital systems design. System-on-chip design with HDL. Description of processors in HDL. Description of buses in HDL. Energy-efficient embedded systems design. Design of communication for embedded computer systems.  High-level synthesis (HLS): data flow and transformation graph, architecture synthesis (allocation, resource sharing, optimization of hardware complexity and performance), operation scheduling (time and resource limited scheduling, heuristic algorithms for scheduling operations). FPGA architecture. Use of software environments intended for FPGAs from different vendors: Xilinx, Altera. Digital system design and simulation in Xilinx Vivado Design Suite. Creating test-bench programs and setting simulation parameters. Synthesis and implementation of a digital system: analysis of time characteristics and used area of ​​an FPGA chip. Programming of FPGA devices. Application of digital systems, implemented in FPGA.
12. Learning methods:

Lectures, independent learning, independent work on project tasks and preparation of seminar papers.
13. Total number of course hours 180
14. Distribution of course hours 3 + 3
15. Forms of teaching 15.1 Lectures-theoretical teaching 45 hours
15.2 Exercises (laboratory, practice classes), seminars, teamwork 45 hours
16. Other course activities 16.1 Projects, seminar papers 30 hours
16.2 Individual tasks 30 hours
16.3 Homework and self-learning 30 hours
17. Grading
17.1 Exams 10 points
17.2 Seminar work/project (presentation: written and oral) 50 points
17.3. Activity and participation 0 points
17.4. Final exam 40 points
18. Grading criteria (points) up to 50 points 5 (five) (F)
from 51 to 60 points 6 (six) (E)
from 61 to 70 points 7 (seven) (D)
from 71 to 80 points 8 (eight) (C)
from 81 to 90 points 9 (nine) (B)
from 91 to 100 points 10 (ten) (A)
19. Conditions for acquiring teacher’s signature and for taking final exam Regular attendance at classes and prepared seminar work.
20. Forms of assessment

During the semester, tests are conducted during the classes. Written exam is taken for a maximum of 120 minutes at the end of the semester or in exam sessions. A seminar paper or project task (team or individual) is prepared. The final grade includes points from the exam, tests and from the seminar paper or project assignment. A special instruction published before each exam regulates the manner of taking the exam and the use of teaching aids and electronic devices during the exam.
21. Language Macedonian and English
22. Method of monitoring of teaching quality Self-evaluation
23. Literature
23.1. Required Literature
No. Author Title Publisher Year
1. João M. P. Cardoso, Michael Hübner Reconfigurable Computing: From FPGAs to Hardware/Software Codesign Springer 2011
2. Eduardo Augusto Bezerra, Djones Vinicius Lettnin Synthesizable VHDL Design for FPGAs Springer 2014
3. Cem Unsalan, Bora Tar Digital System Design with FPGA: Implementation Using Verilog and VHDL Mc Graw Hill 2017
23.2. Additional Literature
No. Author Title Publisher Year
1.  Douglas L. Perry  VHDL : Programming By Example, Fourth Edition  McGraw-Hill  2002
2.  Brock J. LaMeres    Quick Start Guide to Verilog  Springer  2019