| 1. | Course Title | VLSI Design | |||||||||||
| 2. | Code | 4ФЕИТ05004 | |||||||||||
| 3. | Study program | 16-MNT | |||||||||||
| 4. | Organizer of the study program (unit, institute, department) | Faculty of Electrical Engineering and Information Technologies | |||||||||||
| 5. | Degree (first, second, third cycle) | Second cycle | |||||||||||
| 6. | Academic year/semester | I/1 | 7. | Number of ECTS credits | 6.00 | ||||||||
| 8. | Lecturer | Dr Katerina Raleva | |||||||||||
| 9. | Course Prerequisites | ||||||||||||
| 10. | Course Goals (acquired competencies):
This course offers an overview to the entire VLSI design process, focusing on the latest solutions for System-on-Chip (SoC) and IP-based design. |
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| 11. | Course Syllabus:
Hierarchical approach in VLSI design of digital integrated circuits. CMOS technology. Logic gates and combinational networks in CMOS technology. Propagation delay estimation of logic gate and combinational network. Models of interconnection networks. Delay in interconnections. Combinational logic tests. Power optimization. Sequential networks – Latches and flip-flops in CMOS technology. Timing parameters (setup and hold time). Rules for designing sequential networks with logic gates and memory elements (a clocking discipline). Calculation of maximum clock frequency. Finite state machine – techniques for good implementation and validation of the selected design. Overview of basic types of components as subsystems – basic design concepts. Distribution of chip subsystems (floorplanning) – Power distribution. Clock distribution. Architecture Design – Hardware description languages. RTL (Register-Transfer Level) design. Pipelining design. GALS (Globally Asynchronous, Locally Synchronous) design. Designing chips with IP (Intellectual Property). IP components – selection and implementation in the design. |
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| 12. | Learning methods:
lectures with presentations, homework and project assignment |
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| 13. | Total number of course hours | 180 | |||||||||||
| 14. | Distribution of course hours | 3 + 3 | |||||||||||
| 15. | Forms of teaching | 15.1 | Lectures-theoretical teaching | 45 hours | |||||||||
| 15.2 | Exercises (laboratory, practice classes), seminars, teamwork | 45 hours | |||||||||||
| 16. | Other course activities | 16.1 | Projects, seminar papers | 30 hours | |||||||||
| 16.2 | Individual tasks | 30 hours | |||||||||||
| 16.3 | Homework and self-learning | 30 hours | |||||||||||
| 17. | Grading | ||||||||||||
| 17.1 | Exams | 30 points | |||||||||||
| 17.2 | Seminar work/project (presentation: written and oral) | 30 points | |||||||||||
| 17.3. | Activity and participation | 10 points | |||||||||||
| 17.4. | Final exam | 30 points | |||||||||||
| 18. | Grading criteria (points) | up to 50 points | 5 (five) (F) | ||||||||||
| from 51 to 60 points | 6 (six) (E) | ||||||||||||
| from 61 to 70 points | 7 (seven) (D) | ||||||||||||
| from 71 to 80 points | 8 (eight) (C) | ||||||||||||
| from 81 to 90 points | 9 (nine) (B) | ||||||||||||
| from 91 to 100 points | 10 (ten) (A) | ||||||||||||
| 19. | Conditions for acquiring teacher’s signature and for taking final exam | completed homework and project assignments | |||||||||||
| 20. | Forms of assessment | written final exam and oral presentation of the final project | |||||||||||
| 21. | Language | Macedonian and English | |||||||||||
| 22. | Method of monitoring of teaching quality | internal evaluation and surveys | |||||||||||
| 23. | Literature | ||||||||||||
| 23.1. | Required Literature | ||||||||||||
| No. | Author | Title | Publisher | Year | |||||||||
| 1. | Wayne Wolf | Modern VLSI Design: An IP-Based Design, 4th Edition | Prentice Hall | 2009 | |||||||||
| 2. | Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic | Digital Integrated Circuits: A Design Perspectives 2nd Edition | Pearson | 2005 | |||||||||
| 23.2. | Additional Literature | ||||||||||||
| No. | Author | Title | Publisher | Year | |||||||||
| 1. | Wayne Wolf | Modern VLSI Design: System-on-Chip Design | Prentice Hall | 2002 | |||||||||
