VLSI Design with PLD and FPGA components

Објавено: October 12, 2018
  1.    Course Title VLSI Design with PLD and FPGA components
  2.    Code 3ФЕИТ05З001
  3.    Study program KHIE, KTI
  4.    Organizer of the study program (unit, institute, department) Faculty of Electrical Engineering and Information Technologies
  5.    Degree (first, second, third cycle) First cycle
  6.    Academic year/semester IV/7   7.    Number of ECTS credits 6.00
  8.    Lecturer Dr Katerina Raleva
  9.    Course Prerequisites

10.    Course Goals (acquired competencies):  Knowledge of the concept of programmable components (programmable logic devices and FPGAs). Knowledge of VHDL. Able to design complex logic circuits and systems with VHDL and to be synthesized on a FPGA development board.

11.    Course Syllabus: VLSI design and the need of hardware description languages. Available IC technologies. Simple programmable logic devices: PAL, GAL, PLA. Programming technologies. Architecture of CPLD – array-based and multiplexer-based interconnects, product-term distribution, macrocell structure. FPGA – basic characteristics and architecture. Implementation of combinational logic in CLB. Overview of the architecture of commercially available FPGA (Xilinx and Altera). VHDL structure – entity and architecture. Signals, data and variables. Concurrent and sequential statements. Creating combinational and synchronous logic using VHDL.Datapath components.State machine design. RTL design. Hierarchy in large designs. Mixed-signal programmable components.
12.    Learning methods:
13.    Total number of course hours 3 + 1 + 1 + 0
14.    Distribution of course hours 180
15.    Forms of teaching 15.1. Lectures-theoretical teaching 45
15.2. Exercises (laboratory, practice classes), seminars, teamwork 30
16.    Other course activities 16.1. Projects, seminar papers 10
16.2. Individual tasks 15
16.3. Homework and self-learning 70
17.    Grading 17.1. Exams 20
17.2. Seminar work/project (presentation: written and oral) 10
17.3. Activity and participation 10
17.4. Final exam 60
18.    Grading criteria (points) up to 50 points     5 (five) (F)
from 51 to 60 points     6 (six) (E)
from 61 to 70 points     7 (seven) (D)
from 71 to 80 points     8 (eight) (C)
from 81 to 90 points     9 (nine) (B)
from 91 to 100 points   10 (ten) (A)
19.    Conditions for acquiring teacher’s signature and for taking final exam Lectures and tutorials attendance and successful completion of lab exercises.
20.  Forms of assessment During the semester, two partial written exams are provided (at the middle and at the end of the semester, lasting 120 minutes) and a test of laboratory exercises (after the exercises). The final grade includes the points from the partial exams, the points from the homework assignments, the points from the laboratory exercises and the points from the final project work.
In the planned exam sessions, a written exam is taken (duration 180 minutes). The final grade includes the points from the written exam, the points from the homework assignments, the points from the laboratory exercises and the points from the final project work.
The final project work should be finished and presented no more then 2 week after the end of semester.
It is not allowed to use books, scripts, manuscripts or notes of any kind during the exam, as well as a calculator, mobile phone, tablet or any other electronic device
21.   Language Macedonian and English
22.  Method of monitoring of teaching quality Internal evaluation and surveys.
23.    Literature
23.1. Required Literature
No. Author Title Publisher Year
1 Kevin Skahill VHDL for Programmable Logic Pearson Education 2006
23.2. Additional Literature
No. Author Title Publisher Year
1 Frank Vahid  Digital Design  John Wiley & Sons, Inc.  2007
2  S. D. Brown  and  Z. G. Vranesic  Fundamentals of Digital Logic with VHDL Design  McGraw-Hill  2005