1. | Course Title | From Microelectronics to Nanoelectronics | |||||||||||
2. | Code | 4ФЕИТ05020 | |||||||||||
3. | Study program | 9-VMS, 16-MNT | |||||||||||
4. | Organizer of the study program (unit, institute, department) | Faculty of Electrical Engineering and Information Technologies | |||||||||||
5. | Degree (first, second, third cycle) | Second cycle | |||||||||||
6. | Academic year/semester | I/1 | 7. | Number of ECTS credits | 6.00 | ||||||||
8. | Lecturer | Dr Katerina Raleva | |||||||||||
9. | Course Prerequisites | ||||||||||||
10. | Course Goals (acquired competencies):
The course offers a thorough knowledge on micro- and nano-technologies and the ability to understand the limits of electronic design with scaling of CMOS technology and the new transistor architectures. The student will be able to apply the new nanoscale transistors and memories in the design of electronic circuits and systems. |
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11. | Course Syllabus:
Introduction to microelectronics fabrication (lithography, diffusion, etching, ion implantation, metallization, packaging). Theory of MOS capacitor. Physics of MOSFET – long channel and short channel devices. Scaling MOSFET – physical effects in deep sumbicromenter devices. CMOS technology. Scaling MOSFET and Moore’s Law. Limits of CMOS scaling- bulk CMOS ans SOI CMOS. New transistor architectures: fully-depleted SOI, dual-gate, FinFET, gate-all-around transistors. Semiconductor memories (SRAM, DRAM, flash). Integration of technologies. BiCMOS-process, integrated optoelectronics. Introductory concept of nanotechnology. Nanomaterials and nanostructures fabrication techniques (top-down, bottom-up, self-assembly). Nanoelectronics: single electron transistor, nanowire and carbon nanotube transistors, ReRAM, few electron memories. |
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12. | Learning methods:
lectures with presentations, homework and project assignment |
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13. | Total number of course hours | 180 | |||||||||||
14. | Distribution of course hours | 3 + 3 | |||||||||||
15. | Forms of teaching | 15.1 | Lectures-theoretical teaching | 45 hours | |||||||||
15.2 | Exercises (laboratory, practice classes), seminars, teamwork | 45 hours | |||||||||||
16. | Other course activities | 16.1 | Projects, seminar papers | 30 hours | |||||||||
16.2 | Individual tasks | 30 hours | |||||||||||
16.3 | Homework and self-learning | 30 hours | |||||||||||
17. | Grading | ||||||||||||
17.1 | Exams | 40 points | |||||||||||
17.2 | Seminar work/project (presentation: written and oral) | 50 points | |||||||||||
17.3. | Activity and participation | 10 points | |||||||||||
17.4. | Final exam | 0 points | |||||||||||
18. | Grading criteria (points) | up to 50 points | 5 (five) (F) | ||||||||||
from 51 to 60 points | 6 (six) (E) | ||||||||||||
from 61 to 70 points | 7 (seven) (D) | ||||||||||||
from 71 to 80 points | 8 (eight) (C) | ||||||||||||
from 81 to 90 points | 9 (nine) (B) | ||||||||||||
from 91 to 100 points | 10 (ten) (A) | ||||||||||||
19. | Conditions for acquiring teacher’s signature and for taking final exam | homework and project assignment | |||||||||||
20. | Forms of assessment | written tests and oral presentation of final project | |||||||||||
21. | Language | Macedonian and English | |||||||||||
22. | Method of monitoring of teaching quality | internal evaluation and surveys | |||||||||||
23. | Literature | ||||||||||||
23.1. | Required Literature | ||||||||||||
No. | Author | Title | Publisher | Year | |||||||||
1. | Yuan Taur and Tak H. Ning | Fundamentals of Modern VLSI Devices, 2nd edition | Cambridge University Press | 2013 | |||||||||
2. | Neil H.E. Weste and David Harris | CMOS VLSI Design | Pearson Education, Inc. | 2005 | |||||||||
3. | edited by Shunri Oda and David K. Ferry | Nanoscale Silicon Devices | CRC Press | 2016 | |||||||||
23.2. | Additional Literature | ||||||||||||
No. | Author | Title | Publisher | Year | |||||||||
1. | R.F. Pierret | Field Effect Devices (Volume 4 on Modular Series on Solid State Devices) | Prentice Hall | 2001 | |||||||||
2. | Konstantin Likarev | Single Electron Devices and Their Applications (a review paper) | Proc. IEEE, vol. 87, pp. 606-632 | 1999 |