1. | Course Title | From Microelectronics to Nanoelectronics | |||||||||||||||
2. | Code | 4ФЕИТ05020A | |||||||||||||||
3. | Study program | 16-МНТ, 9-ВМС | |||||||||||||||
4. | Organizer of the study program (unit, institute, department) | Faculty of Electrical Engineering and Information Technologies
Ss. Cyril and Methodius University in Skopje |
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5. | Degree (first, second, third cycle) | Second cycle | |||||||||||||||
6. | Academic year/semester | Year | 1 | Semester | 1 | ||||||||||||
7. | Workload measured by number of ECTS credits | 6 | |||||||||||||||
8. | Lecturer (In case of several lecturers to note the responsible one) | 180 | |||||||||||||||
9. | Language of teaching | Macedonian and English | |||||||||||||||
10. | Course Prerequisites | None | |||||||||||||||
11. | Course Goals (acquired competencies) and study results:
The course offers a thorough knowledge on micro- and nano-technologies and the ability to understand the limits of electronic design with scaling of CMOS technology and the new transistor architectures. After the completion of the course, the student will understand the differences between micro and nanofabrication, the process steps in microfabrication and the possibilities of integration of technologies. He/she will know the physics of MOS capacitor and MOSFET and understand the new architectures and materials for nanoscale transistors. The student will also have a deeper knowledge in the internal structure of basic semiconductor memories and the understanding of emerging memories. Finally, with these study results,the student will be able to apply the new nanoscale transistors and memories in the design of electronic circuits and systems. |
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12. | Course Syllabus (with Chapters) and study results for each chapter:
Chapter 1 Introduction to microelectronics fabrication Planar Si technology. Process steps: lithography, diffusion, etching, ion implantation, metallization, packaging. Process steps for designing npn and pnp transistors and n-channel and p-channel MOSFETs. Microfabricaton of CMOS inverter (p well and n-well process, twin-well process). Electrical isolation of elements in CMOS processes – STI (Shallow Trench Isolation) and LOCOS (Local Oxiation of Silicon). Latch-up in CMOS integrated circuits. Limits of CMOS scaling- bulk CMOS and SOI CMOS. 3D integration. Integration of technologies. BiCMOS process, integrated optoelectronics. Study results: a deep understanding of planar silicon technology fabrication and CMOS process steps, limits of CMOS scaling and the possibilities of integration of technologies. Chapter 2. Layout design rules CMOS IC design flow. Lambda design rules. Design of CMOS layout. Stick diagram. Stick diagrams for basic and complex logic gates. Study results: The students will be able to design a CMOS layout of simple and complex logic gates. Chapter 3. MOS Capacitor and MOSFET Theory of MOS capacitor (accumulation, depletion, weak inversion and inversion, C-V characteristic). Physics of MOSFET – theory of long channel and short channel devices. Scaling MOSFET and Moore’s Law. New transistor architectures: fully-depleted SOI, dual-gate, FinFET, gate-all-around transistors. Study results: The students will have a deeper knowledge in the physics of MOS capacitor and planar MOSFET and understands the new transistor architectures. Chapter 4. Semiconductor memories and new emerging memories Internal structure of SRAM and DRAM – SRAM vs DRAM memory cell. Sense amplifier. Circuit for precharge and equalization. Read and write operation of one bit. Timing diagrams for read and write operation for SRAM and DERAM. EEPROM and flash memory – FAMOS (Floating Gate Avalanche MOS). EEPROM memory cell and conventional flash memory cell. Read and write operation in EEPROM and flash (Fowler-Nordheim tunneling and injection of hot electrons) Internal structure of NOR and NAND memory flash area. New emerging memories. Study results: a deeper knowledge in the internal structure of basic semiconductor memories and the understanding of emerging memories. Chapter 5. Nanotechnologies and Nanoelectronics Introductory concept of nanotechnology. Nanomaterials and nanostructures fabrication techniques (top-down, bottom-up, self-assembly). Nanoelectronics: single electron transistor, nanowire and carbon nanotube transistors, few electron memories. Study results: an understanding of nanostructure fabrication techniques and the concepts of nanoelectronic devecies and memories |
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13. | Interconnection of Courses: As part of the hardware design group for embedded and IoT systems, this course is connected to the courses: Techniques for designing dedicated computer systems, Advanced Operating Systems Concepts, Dedicated Processors, Contemporary Microcontrollers for Embedded Systems Design, Techniques for HDL Design and FPGA Implementation, Programming Embedded Systems in ‘C’. | ||||||||||||||||
14. | Detailed description of teaching and work methods: Lecturing, consultations, independent work on course project tasks and preparation of seminar papers, presentations of the work | ||||||||||||||||
15. | Total number of course hours | 180 | |||||||||||||||
16.
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Forms of teaching
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16.1 | Lectures-theoretical teaching | 45 hours
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16.2 | Exercises (laboratory, practice classes), seminars, teamwork | 45 hours
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16.3 | Practical work (hours): | 0 hours | |||||||||||||||
17.
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Other course activities
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17.1 | Projects, seminar papers | 45 hours | |||||||||||||
17.2 | Individual tasks | 0 hours | |||||||||||||||
17.3 | Homework and self-learning | 45 hours | |||||||||||||||
18. | Conditions for acquiring teacher’s signature and for taking final exam: 60% of all required course activities | ||||||||||||||||
19. | Grading | ||||||||||||||||
19.1 | Quizzes | 20 points | |||||||||||||||
19.2 | Seminar work/project (presentation: written and oral) | 50 points | |||||||||||||||
19.3 | Final Exam | 30 points | |||||||||||||||
20. | Grading criteria (points) | up to 50 points | 5 (five) (F) | ||||||||||||||
from 51 to 60 points | 6 (six) (E) | ||||||||||||||||
from 61 to 70 points | 7 (seven) (D) | ||||||||||||||||
from 71 to 80 points | 8 (eight) (C) | ||||||||||||||||
from 81 to 90 points | 9 (nine) (B) | ||||||||||||||||
from 91 to 100 points | 10 (ten) (A) | ||||||||||||||||
21. | Method of monitoring of teaching quality | Self-evaluation and student surveys | |||||||||||||||
22. | Literature | ||||||||||||||||
22.1. | Required Literature | ||||||||||||||||
No. | Author | Title | Publisher | Year | |||||||||||||
1. | Yuan Taur and Tak H. Ning | Fundamentals of Modern VLSI Devices (2nd Edition) | Cambridge University Press | 2009 | |||||||||||||
2. | Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic | Digital Integrated Circuits: A Design Perspective (2nd Edition) | Prentice Hall | 2005 | |||||||||||||
22.2. | Additional Literature | ||||||||||||||||
No. | Author | Title | Publisher | Year | |||||||||||||
1. | R.F. Pierret | Field Effect Devices (Volume 4 on Modular Series on Solid State Devices) | Prentice Hall | 2001 | |||||||||||||
2. | Konstantin K. Likharev | Single Electron Devices and Their Applications (a review paper) | Proc. IEEE, vol. 87, pp. 606-632 | 1999 |