Данијела Ефнушева

E-maildanijela@feit.ukim.edu.mk
Телефон+ 389 2 3099 177

Работно искуство

Раководител на Лабораторија за Компјутерски технологии и инженерство (од февруари 2020)
Доцент (од март 2018)
Асистент (октомври 2014 – февруари 2017)
Помлад асистент (ноември 2011 – септември 2014)

Образование

Доктор на технички науки, насока: Електротехника и информациски технологии (декември 2011 – декември 2017, Универзитет “Св. Кирил и Методиј”, Факултет за електротехника и информациски технологии – Скопје, Македонија),
Докторски труд: “Проектирање и практична реализација на RISC-базирана мемориско-центрична
процесорска архитектура и нејзина примена”, просечна оцена 10.00

Магистер по електротехника и информациски технологии, насока: Компјутерски мрежи и е-
технологии (октомври 2008 – јуни 2010, Универзитет “Св. Кирил и Методиј”, Факултет за електротехника и информациски технологии – Скопје, Македонија)
Магистерски труд: “Развој на архитектура на мрежен процесор за работа во повеќегигабитни мрежи”, просечна оцена 10.00

Дипломиран инженер по електротехника и информациски технологии, насока: Информатика и
компјутерско инженерство (октомври 2004 – септември 2008)

Институт

Компјутерски технологии и инженерство

Објавени трудови

[1] Danijela Efnusheva, “Performance Evaluation of RISC-based Memory-centric Processor

Architecture”, Advances in Intelligent Systems and Computing, Springer (ISSN 2194-5357), April,

[2] Aleksandar Trenchevski, Marija Kalendar, Hristijan Gjoreski, Danijela Efnusheva, “Prediction of

Air Pollution Concentration Using Weather Data and Regression Models”, Proceedings of

International Conference on Applied Innovations in IT, Volume 8, Issue 1, Koethen, Germany,

March, 2020, pp. 55-61.

[3] Danijela Efnusheva, Ana Cholakoska, Marija Kalendar, “FPGA design of IP packet filter based

on SNORT rules”, Proceedings of 10th International Conference on Information Society and

Technology – ICIST 2020, Kopaonik, Serbia, March, 2020.

[4] Danijela Efnusheva, “Performance Evaluation of Hardware Unit for Fast IP Packet Header

Parsing”, Advances in Intelligent Systems and Computing, Springer (ISSN 2194-5357), October,

2019 (accepted for publication).

[5] Danijela Efnusheva, “FPGA Implementation of RISC-based memory-centric processor

architecture”, International Journal of Advanced Computer Science and Applications(IJACSA),

Volume 10, Issue 9, ISSN 2156-5570 (Online), 2019.

[6] Ana Cholakoska, Danijela Efnusheva, Marija Kalendar, “Hardware Implementation of IP Packet

Filtering in FPGA”, Proceedings of International Conference on Applied Innovation in IT, Volume

7, Issue 1, pp. 23-29.

[7] Dejan Vasilevski, Ana Cholakoska, Marija Kalendar, Danijela Efnusheva, ” Managing real time

IoT data with cloud computing services”, Proceedings of XIV International Conference ETAI 2018,

Struga, Macedonia, September, 2018.

[8] Danijela Efnusheva, Ana Cholakoska, Aristotel Tentov, “A survey of different approaches for

overcoming the processor-memory bottleneck”, International Journal of Computer Science &

Information Technology, Vol 9, No. 2, April 2017.

[9] Danijela Efnusheva, Aristotel Tentov, “Design of Processor in Memory with RISC-modifed

Memory-centric Architecture”, Advances in Intelligent Systems and Computing, Springer (ISSN

2194-5357), April, 2017.

[10] Danijela Efnusheva, Aristotel Tentov, Ana Cholakoska, Marija Kalendar, “FPGA Implementation

of IP Packet Header Parsing Hardware”, Proceedings of Fifth International Conference on Applied

Innovations in IT, Koethen, Germany, March 16, 2017, pp. 33-40.

[11] Danijela Efnusheva, Ana Cholakoska, Aristotel Tentov, “Design of Reconfigurable Memory for

Fast Network Packet Header Parsing”, Proceedings of 7th International Conference on

Information Society and Technology – ICIST 2017, Kopaonik, Serbia, March, 2017.

[12] Danijela Efnusheva, Goce Dokoski, Aristotel Tentov, Marija Kalendar, “Memory-centric

approach of network processing in a modified RISC-based processing core”, Proceedings of IEEE

Future Technologies Conference, San Francisco, CA, USA, December, 2016, pp. 1181-1188.

[13] Danijela Efnusheva, Marija Kalendar, Aristotel Tentov, Goce Dokoski, “A modified memory

centric approach for network packet processing”, Proceedings of XIII International Conference

ETAI 2016, Ohrid, Macedonia, September, 2016.

[14] Danijela Efnusheva, Goce Dokoski, Aristotel Tentov, Marija Kalendar, “Проектирање на нова

мемориско-центрична архитектура и организација на процесори”, Proceedings of XII

International Conference ETAI 2015, Ohrid, Macedonia, September 24-26, 2015, pp. EI-4.

[15] Goce Dokoski, Danijela Efnusheva, Aristotel Tentov, Marija Kalendar, “Софтверска околина

за мемориско-центрична процесорска архитектура”, Proceedings of XII International

Conference ETAI 2015, Ohrid, Macedonia, September 24-26, 2015, pp. EI-4.

[16] Danijela Efnusheva, Goce Dokoski, Aristotel Tentov, Marija Kalendar, “A novel memory-centric

architecture and organization of processors and computers”, Proceedings of Third International

Conference on Applied Innovations in IT, Koethen, Germany, March 19, 2015, pp. 47-53.

[17] Goce Dokoski, Danijela Efnusheva, Aristotel Tentov, Marija Kalendar, “Software for explicitly

parallel memory-centric processor architecture”, Proceedings of Third International Conference

on Applied Innovations in IT, Koethen, Germany, March 19, 2015, pp. 37-40.

[18] Danijela Efnusheva, Aristotel Tentov, Natasha Tagasovska, “An efficient 64-point IFFT hardware

module design”, New Trends in Networking, Computing, E-learning, Systems Sciences, and

Engineering, Bridgeport, USA, Springer (ISBN 978-3-319-06764-3), November 2014, pp. 463 – 470.

[19] Natasha Tagasovska, Paulina Grnarova, Aristotel Tentov, Danijela Efnusheva, “Performances

of LEON3 IP Core in WiGig environment on receiving side”, New Trends in Networking,

Computing, E-learning, Systems Sciences, and Engineering, Bridgeport, USA, Springer (ISBN

978-3-319-06764-3), November 2014, pp. 243-251.

[20] Danijela Efnusheva, Natasha Tagasovska, Aristotel Tentov, Marija Kalendar, “Efficiency

comparison of DFT/IDFT algorithms by evaluating diverse hardware implementations,

parallelization prospects and possible improvements”, Proceedings of Second International

Conference on Applied Innovations in IT, Koethen, Germany, March 26-27, 2014, pp. 11-20.

[21] Danijela Efnusheva, Aristotel Tentov, “Integrating processing in RAM memory and its application

to high speed FFT computation”, Proceedings of 4th International Conference on Information

Society and Technology – ICIST 2014, Serbia, March 9-13, 2014, pp. 382-387.

[22] Danijela Efnusheva, Josif Kjosev, Katerina Raleva, “Exploring the use of Cadence IC in

education”, International Journal of Electronics, Volume 17, Number 2, Dec. 2013, pp. 89-94.

[23] Danijela Efnusheva, Goce Dokoski, Aristotel Tentov, Marija Kalendar, “Different Approaches for

OFDM Transmitter and Receiver Design in Hardware, FPGA Design and Implementation with

Performance Comparison”, International Journal of Advanced Research in Computer Science

and Software Engineering (ISSN 2277-128X), Volume 3, Issue 10, October 2013, pp. 1163-1172.

[24] Danijela Efnusheva, Aristotel Tentov, “Hardware implementation of 64-point FFT module in

FPGA”, Proceedings of XI International Conference ETAI 2013, Ohrid, Macedonia, September

26-28, 2013, pp. EI-4.

[25] Danijela Efnusheva, Josif Kjosev and Katerina Raleva, “Educational Aspects of Cadence IC”,

Proceedings of XI International Conference ETAI 2013, Ohrid, Macedonia, September 26-28,

2013, pp. E3-4.

[26] Riste Oreshkovski, Ilija Dzopkovski, Aristotel Tentov and Danijela Efnusheva, “Practical

Approach to 8086 Based Multiprocessor System Design”, Proceedings of XI International

Conference ETAI 2013, Ohrid, Macedonia, September 26-28, 2013, pp. EI-6.

[27] Jakimovska Danijela, Jakimovski Goran, Tentov Aristotel, Bojchev Dimitar, “Performance

Estimation of Parallel Processing Techniques on Various Platforms”, Proceedings of 20th

Telecommunications forum – TELFOR 2012, Belgrade, Serbia, November 20-22, 2012, pp. 1409

– 1412.

[28] Danijela Jakimovska, Aristotel Tentov, Goran Jakimovski, Sashka Gjorgjievska, Maja Malenko,

“Modern Processor Architectures Overview”, Proceedings of XVIII International Scientific

Conference on Information, Communication and Energy Systems and Technologies – ICEST

2012, V. Tarnovo, Bulgaria, June 28-30, 2012, pp. 194-197.

[29] Данијела Јакимовска, Сашка Ѓорѓиевска, Аристотел Тентов, “Имплементација на

Интеловиот Микропроцесор 8085 со употреба на LISA”, Proceedings of Xта Меѓународна

Конференција ETAI2011, 16-20 септември 2011, Охрид, Р. Македонија, pp. I3-2.

[30] Sashka Gjorgjievska, Danijela Jakimovska, Aristotel Tentov, “LISA Implementation and

Extension of the DLX Processor Architecture”, Proceedings of Xth International Conference

ETAI2011, 16-20 September 2011, Ohrid, R. Macedonia, pp. I3-1.

[31] D. Jakimovska, A. Tentov, S. Gjorgjievska, G. Dokoski, M. Kalendar, “Performance Estimation

of Novel 32-bit and 64-bit RISC based Network Processor Cores”, Cyber Journals:

Multidisciplinary Journals in Science and Technology, Journal of Selected Areas in

Telecommunications (JSAT), May Edition, 2011, pp. 28 – 40.

[32] Marija Kalendar, Danijela Jakimovska, Aristotel Tentov, Goce Dokoski, “Novel Processor

Architecture for Modified Advanced Routing in NGN”, Proceedings of 26th ACM Symposium On

Applied Computing – ACM SAC 2011, 21-24 March, Taichung, Taiwan, pp. 486 – 491.

[33] Jakimovska Danijela, Dokoski Goce, Kalendar Marija, Tentov Aristotel, “Design and HDL

implementation of original 64 – bit network processor core”, Proceedings of XVIII

Telecommunications Forum – TELFOR 2010, 23-25 November, Belgrde, R.Serbia, pp. 155 – 158.

[34] Kalendar Marija, Jakimovska Danijela, Tentov Aristotel, Dokoski Goce “Advanced Routing

Concept Performance Analysis”, Proceedings of XVIII Telecommunications Forum – TELFOR

2010, 23-25 November, Belgrde, R.Serbia, pp. 139 – 142.

[35] Marija Kalendar, Danijela Jakimovska, Goce Dokoski, Aristotel Tentov, “Advanced Routing

Concept Supported by a Novel Processor Architecture”, Proceedings of VIII International

Symposium on Industrial Electronics – INDEL 2010, 4-6 November, Banja Luka, BiH, pp. 351 – 356

[36] Danijela Jakimovska, Goce Dokoski, Marija Kalendar, Aristotel Tentov, “Network processor

architecture design for multi-gigabit networks”, Proceedings of VIII International Symposium on

Industrial Electronics – INDEL 2010, 4-6 November, Banja Luka, BiH, pp. 357 – 362.

[37] Marija Kalendar, Aristotel Tentov, Danijela Jakimovska, Goce Dokoski, “A Novel Flow Based

Approach in Routing Decision Mechanism”, Proceedings of 3rd IASTED International Multi

conference on Automation, Control, and Information Technology (ACIT2010), 15-18 June 2010,

Novosibirsk, Russia, pp. 158-163.

[38] Marija Kalendar, Aristotel Tentov, Danijela Jakimovska, Goce Dokoski, “Modified IP Routing

Process, Supported by New Network Processor Architecture”, Proceedings of ETRAN 2010, 54th

Conference for Electronics, Telecommunications, Computers, Automatic control and Nuclear

engineering, 7-11 June 2010, Donji Milanovac, R. Serbia, pp. RT3.7-1-4.

[39] D. Jakimovska, G. Dokoski, A. Tentov, M. Kalendar, “Network processors: evolution and trends”,

Proceedings of IXth National Conference with International Participation ETAI2009, 26-29

September 2009, Ohrid, R. Macedonia, pp. IE2-4.